1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a gate electrode of a MOSFET, and more particularly to a method of forming a gate electrode with a polycide structure in semiconductor device.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 .mu.m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysiliocn layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a polycide structure in which a silicide layer using a refractory metal such as tungsten(W) and titanium(Ti) is formed on the polysilicon layer, has been researched.
FIG. 1A to FIG. 1C show a method of forming a gate electrode with a titanium polycide structure in accordance with a prior art.
As shown in FIG. 1A, a gate oxide layer 11 is grown on a semiconductor substrate 10 and a doped polysilicon layer 12 deposited thereon.
As shown in FIG. 1B, a titanium silicide(TiSi.sub.x) layer of an amorphous phase is deposited on the polysilicon layer 12 by physical vapor deposition(PVD) using TiSix target. Next, the TiSi.sub.x layer of the amorphous phase is thermal-treated by rapid thermal processing(RTP) at a selected temperature for several seconds, to be transformed into a titanium silicide(TiSi.sub.2) layer 13 of a crystalline phase.
As shown in FIG. 1C, an oxide(or nitride) layer 14 is formed on the TiSi.sub.2 layer 13, for a self-aligned contact(SAC) process which will be performed after. The oxide layer 14, the TiSi.sub.2 layer 13, the polysilicon layer 12 and the gate oxide layer 11 are patterned by photolithography and etching process to form a gate electrode.
Conventionally several thermal processes such as a first thermal process for gate re-oxidation, a second thermal process for forming source/drain, a third thermal process for planarizing a intermediate insulating layer and a fourth thermal process for forming a capacitor and the like, are performed subsequently, after forming the gate electrode as above described.
FIG. 2 shows a cross sectional view of a gate electrode with a titanium polycide structure in which a TiSi.sub.2 layer 23 is formed on a polysilicon layer 22 according to the prior art. However, when performing above thermal processes respectively, the TiSi.sub.2 layer 23 is agglomerated to generate stress, so that Ti of TiSi.sub.2 layer 23 is diffused into the polysilicon layer 22 and reacted with Si of the polysilicon layer 22, thereby deteriorating the interface roughness between the polysilicon layer 22 and the TiSi.sub.2 layer 23(TiSi.sub.2 layer/polysilicon layer), as shown in FIG. 2, after performing above thermal processes.
Furthermore, in case the interface roughness is extremely deteriorated, the TiSi.sub.2 layer 23 comes in contact with a gate oxide layer 21, thereby deteriorating the property of the gate oxide layer 21. As a result, the reliability of a device is deteriorated.
As not above described, in FIG. 2, reference numbers 20, 24, 25 and 26 indicate a silicon substrate, a mask oxide layer, a spacer oxide layer and source/drain regions, respectively.
Moreover, although described on the gate electrode with the titanium polycide structure, these problems mostly occur in gate electrode with a polycide structure.